MC68HC705MC4 Datasheet, PDF (44/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
Writing to either of the Port B registers could corrupt the SCI data. See SECTION 10:
SERIAL COMMUNICATIONS INTERFACE for a discussion of the SCI subsystem.
Read $0005
Write $0005
Write $0001
Reset
(RST)
Data Direction
Register Bit
Data
Register Bit
I/O
Output
Pin
Read $0001
Internal HC05
Data Bus
Figure 6-3: Port B I/O Circuitry
6.3 PORT C
Port C is an 8-bit bidirectional port that has shared pins with the A/D subsystem. The Port
C data register is located at address $0002 and its Data Direction Register (DDR) is
located at address $0006. Reset does not affect the data registers, but clears the DDRs,
thereby setting all of the port pins to input mode. Writing a one to a DDR bit sets the
corresponding port pin to output mode. (See Figure 6-4: Port C I/O Circuitry.)
The ADON bit in register ADSC is used to enable/disable the A/D subsystem. Port C may
be used for general I/O applications when the A/D subsystem is disabled or when all A/D
input channels are not required. Unselected channels revert to general purpose I/O. See
SECTION 7: ANALOG SUBSYSTEM.
Read $0006
Write $0006
Write $0002
Read $0002
Internal HC05
Data Bus
Reset
(RST)
Data Direction
Register Bit
Data
Register Bit
I/O
Output
Pin
Figure 6-4: Port C I/O Circuitry
Section 6: Input/Output Ports
MOTOROLA
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