MC68HC705MC4 Datasheet, PDF (81/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
After a complete character shifts into the receive shift register, the data portion of
the character is transferred to the SCDR, setting the receive data register full
(RDRF) flag. The RDRF flag can be used to generate an interrupt.
10.4.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in
multiple-receiver systems, the MCU can be put into a standby state. Setting the receiver
wakeup enable (RWU) bit in SCI control register 2 (SCCR2) puts the MCU into a standby
state during which receiver interrupts are disabled.
Either of two conditions on the PB5/RDI pin can bring the MCU out of the standby state:
• Idle input line condition — If the PD5/RDI pin is at logic one long enough
for 10 or 11 logic ones to shift into the receive shift register, receiver
interrupts are again enabled.
• Address mark — If a logic one occurs in the most significant bit position
of a received character, receiver interrupts are again enabled.
The state of the WAKE bit in SCCR1 determines which of the two conditions wakes up
the MCU.
10.4.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify the start bit and
to detect noise. Any conflict between noise-detection samples sets the noise flag (NF) in
the SCSR. The NF bit is set at the same time that the RDRF bit is set.
10.4.2.5 Framing Errors
If the data recovery logic does not detect a logic one where the stop bit should be in an
incoming character, it sets the framing error (FE) bit in the SCSR. The FE bit is set at the
same time that the RDRF bit is set.
10.4.2.6 Receiver Interrupts
The following sources can generate SCI receiver interrupt requests:
• Receive Data Register Full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character to the
SCDR.
• Receiver Overrun (OR) — The OR bit in the SCSR indicates that the
receive shift register shifted in a new character before the previous
character was read from the SCDR.
• Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or 11
consecutive logic ones shifted in from the PD5/RDI pin.
MOTOROLA
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Section 10: Serial Communications Interface