MC68HC705MC4 Datasheet, PDF (85/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
10.5.4 SCI Status Register (SCSR)
The SCI status register contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
7
6
5
4
3
2
1
0
SCSR ^{READ: TDRE}
TC
RDRF IDLE
OR
NF
FE
$000D _WRITE:
RESET: 1
1
0
0
0
0
0
—
Figure 10-7: SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty
This clearable, read-only bit is set when the data in the SCDR transfers to the
transmit shift register. TDRE generates an interrupt request if the TIE bit in
SCCR2 is also set. Clear the TDRE bit by reading the SCSR with TDRE set,
and then writing to the SCDR. Reset sets the TDRE bit. Software must initialize
the TDRE bit to logic zero to avoid an instant interrupt request when turning on
the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only bit is set when the TDRE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an interrupt
request if the TCIE bit in SCCR2 is also set. Clear the TC bit by reading the
SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit.
Software must initialize the TC bit to logic zero to avoid an instant interrupt
request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full
This clearable, read-only bit is set when the data in the receive shift register
transfers to the SCI data register. RDRF generates an interrupt request if the
MOTOROLA
Page 76
Section 10: Serial Communications Interface