MC68HC705MC4 Datasheet, PDF (58/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
When the TCMP/TCAP1 bit of TCR is set, input capture function for TCAP1 is inhibited.
After a read of the MSB of the input capture register pair (ICRH1, ICRH2), counter
transfers are inhibited until the respective LSB of the register pair (ICRL1, ICRL2) is also
read. This characteristic forces the minimum pulse period attainable to be determined by
the time required to execute an input capture software routine in an application.
Reading the LSB of the input capture register pair (ICRL1, ICRL2) does not inhibit transfer
of the free-running counter. Again, minimum pulse periods are ones that allow software
to read the LSB of the register pair (ICRL1, ICRL2) and perform needed operations. There
is no conflict between reading the LSB (ICRL1, ICRL2) and the free-running counter
transfer since they occur on opposite edges of the internal clock.
Internal
Clock
16-bit
Free-Running $0FEB
Counter
TCAP
Pin
$0FEC
$0FED
$0FEE
$0FEF
Input
Capture
Latch
(See Note)
Input
Capture
Register
PREVIOUS CAPTURE VALUE
$0FED
Input
Capture
Flag
NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the Input Capture
flag is set during the next T11 timer state.
Figure 8-10: State Timing Diagram for Input Capture
8.4 TIMER CONTROL REGISTER (TCR)
The timer control (TCR) and free-running counter (TMRH, TMRL, ACRH, ACRL) registers
are the only registers of the 16-bit timer affected by reset. The Output Compare port
(TCMP) is forced low after reset and remains low until OLVL is set and a valid Output
Compare occurs.
R
TCR
$0017 _W
7
ICIE2
6
ICIE1
5
TOIE
4
OCIE
3
TCMP
/TCAP1
2
IEDG1
1
IEDG2
0
OLVL
reset ⇒
0
0
0
0
0
X
X
0
Figure 8-11: Timer Control Register (TCR)
Section 8: 16-Bit Timer
MOTOROLA
Page 49