MC68HC705MC4 Datasheet, PDF (54/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
7
6
5
4
3
2
1
0
R
TMRH
$0020 _W
TMRH7
reset ⇒
1
TMRH6
1
TMRH5
1
TMRH4
1
TMRH3
1
TMRH2
1
7
6
5
4
3
2
R
TMRL
$0021 _W
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
reset ⇒
1
1
1
1
1
1
Figure 8-2: Timer Registers (TMRH / TMRL)
TMRH1
1
1
TMRL1
0
TMRH0
1
0
TMRL0
0
7
6
5
4
3
2
1
0
R
ACRH
$0022 _W
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
reset ⇒
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
R
ACRL
$0023 _W
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
reset ⇒
1
1
1
1
1
1
0
Figure 8-3: Alternate Counter Registers (ACRH / ACRL)
ACRL0
0
The Timer Registers and Alternate Counter Registers can be read at any time without
affecting their values. However, the Alternate Counter Registers differ from the Timer
Registers in one respect: a read of the Timer register LSB can clear the Timer Overflow
Flag (TOF). Therefore, the Alternate Counter Registers can be read at any time without
the possibility of missing timer overflow interrupts due to clearing of the TOF. See Figure
8-4: State Timing Diagram for Timer Overflow.
Internal
Clock
16-bit
Free-Runni
ng Counter
$FFFE
$FFFF
$0000
$0001
$0002
Timer
Overflow
Flag (TOF)
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the internal clock followed by reading the LSB of the counter register pair (TMRL).
Figure 8-4: State Timing Diagram for Timer Overflow
The free-running counter is initialized to $FFFC during reset and is a read-only register.
Section 8: 16-Bit Timer
MOTOROLA
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