MC68HC705MC4 Datasheet, PDF (34/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
addresses are specified by the contents of memory locations $0FF8 and $0FF9 for input
capture 2, and by the contents of memory locations $0FF6 and $0FF7 for input capture 1.
4.3.2.2 OUTPUT COMPARE INTERRUPT
The output compare interrupt is generated by the 16-bit timer, as described in SECTION
8: 16-BIT TIMER. The output compare interrupt flag is located in register TSR and its
corresponding enable bit can be found in register TCR. The I-bit in the CCR must be clear
in order for the output compare interrupt to be enabled. The interrupt service routine
address is specified by the contents of memory locations $0FF4 and $0FF5.
4.3.2.3 TIMER OVERFLOW INTERRUPT
The timer overflow interrupt is generated by the 16-bit timer as described in SECTION 8:
16-BIT TIMER. The timer overflow interrupt flag is located in register TSR and its
corresponding enable bit can be found in register TCR. The I-bit in the CCR must be clear
in order for the timer overflow interrupt to be enabled. This internal interrupt will vector to
the interrupt service routine located at the address specified by the contents of memory
locations $0FF4 and $0FF5. The timer overflow and the output compare function share
the same interrupt vector, thus requiring the user to poll interrupt request flags.
4.3.3 SCI INTERRUPT
There are five different SCI interrupt flags that cause an SCI interrupt whenever they are
set and enabled. The interrupt flags are in the SCI Status Register (SCSR), and the
enable bits are in the SCI Control Register 2 (SCCR2). Any of these interrupts will vector
to the same interrupt service routine, located at the address specified by the contents of
memory location $0FF2 and $0FF3. See SECTION 10: SERIAL COMMUNICATIONS
INTERFACE.
4.3.4 CORE TIMER (CTIMER) INTERRUPT
There are two different Core timer interrupt flags that cause a CTIMER interrupt whenever
they are set and enabled. The interrupt flags and enable bits are located in the CTIMER
Control and Status Register (CTCSR). Any of these interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
location $0FF0 and $0FF1. See SECTION 11: CORE TIMER.
Section 4: Interrupts
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