MC68HC705MC4 Datasheet, PDF (26/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
SECTION 3
RESETS
The MCU can be reset from four sources: one external input and three internal reset
conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 3-1:
Reset Block Diagram. The CPU and all peripheral modules will be reset by the RST
signal which is the logical OR of internal reset functions and is clocked by the internal bus
clock. The RESET pin will also be pulled low by internal reset for 4 bus cycles.
RESET
4 cycle
counter
LIR
Address
V_DD
OSC
Data
Address
Illegal
Address
Power-On
Reset
(POR)
COP
Watchdog
(COPR)
Reset
Latch
RST
To CPU and
Peripherals
INTERNAL CLOCK
Figure 3-1: Reset Block Diagram
3.1 EXTERNAL RESET (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt trigger.
The external reset occurs whenever the RESET input is driven below the lower threshold
and remains in reset until the RESET pin rises above the upper threshold. The upper and
lower thresholds are given in SECTION 12: ELECTRICAL SPECIFICATIONS.
3.2 INTERNAL RESETS
The three internally generated resets are the illegal address, the initial Power-On Reset
(POR) function, and the COP watchdog timer function.
3.2.1 ILLEGAL ADDRESS RESET
When an opcode fetch occurs at an address that is not in the RAM or ROM/EPROM the
part automatically resets. The part will also reset when an opcode fetch inadvertantly
occurs at an address within the Self-Check/Bootstrap ROM while the device is in User
mode.
Section 3: Resets
MOTOROLA
Page 17