MC68HC705MC4 Datasheet, PDF (68/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
CS[3:1]
001
010
011
100
101
ME
MSK[3:1]
xxx
xxx
0xx
x11
x0x
PWM1
PWM2
PWM OUTPUT
PORT
PORT
PWM OUTPUT
PWM OUTPUT
PWM OUTPUT
LOGIC ONE
LOGIC ONE
PWM OUTPUT
LOGIC ZERO
PWM3
PORT
PORT
LOGIC ZERO
PWM OUTPUT
PWM OUTPUT
x = DON’T CARE
Figure 9-7: PWM Control Example
9.3 PWM DATA BITS
The pulse width of the PWM waveform is controlled by the two data registers PWMA and
PWMB. Each data register can be accessed from one of two locations, PWMx-D (Direct)
and PWMx-I (Interlock). A write interlock and buffer mechanism is used to permit their
contents to be updated simultaneously, preventing undesirable glitching of the associated
Port A I/O. See 9.5.1: PWM DATA REGISTER.
9.4 PWM DURING RESETS
The PWM subsystem has two types of resets. One is a hardware reset denoted by
RESET. The other is a PWM reset denoted by PRESET.
After a RESET, the user should write to the data registers, RATE, CTL-B, then CTL-A.
This will avoid an erroneous duty cycle from being driven on any of the selected PWM Port
pins.
A PRESET condition is reached by clearing the MEB bit and the CSB[3:1] bits in CTL-B,
then the MEA bit and the CSA[3:1] bits in CTL-A. This disables the PWM subsystem,
resets the 8-bit counters, resets the clock generator, and sets the port pins to the state
defined by the respective Port Data Registers and Data Direction Registers.
The data registers are unaffected by RESET. The CTL Registers are cleared by RESET.
A PRESET does not affect any of the PWM registers.
9.5 PWM OPERATION IN USER MODE
All PWM registers are buffered. The register buffering prevents data written to either the
control or data registers from affecting the PWM cycle underway at the time of the data
Section 9: Pulse Width Modulator
MOTOROLA
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