MC68HC705MC4 Datasheet, PDF (59/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
8.4.1 ICIE2 - INPUT CAPTURE INTERRUPT ENABLE 2
Bit 7, when set, enables input capture 2 interrupts to the CPU. The interrupt will occur at
the same time bit 7 (ICF2) in the TSR register is set.
8.4.2 ICIE1 - INPUT CAPTURE INTERRUPT ENABLE 1
Bit 6, when set, enables input capture 1 interrupts to the CPU. The interrupt will occur at
the same time bit 6 (ICF1) in the TSR register is set.
8.4.3 TOIE - TIMER OVERFLOW INTERRUPT ENABLE
Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The interrupt will
occur at the same time bit 5 (TOF) in the TSR register is set.
8.4.4 OCIE - OUTPUT COMPARE INTERRUPT ENABLE
Bit 4, when set, enables output compare interrupts to the CPU. The interrupt will occur at
the same time bit 4 (OCF) in the TSR register is set.
8.4.5 TCMP/TCAP1
Bit 3, when set, enables the TCMP function, when clear, the TCAP1 function. Reset clears
this bit. When set it enables the TCMP output latch value to be output to the port pin and
disables the edge detect of TCAP1. When clear, it disables the TCMP output latch from
the port pin and enables the edge detect of TCAP1. Note that this bit has no effect on the
setting of OCF and ICF1.
8.4.6 IEDG1 - INPUT CAPTURE EDGE SELECT 1
Bit 2 selects which edge of the input capture signal will trigger a transfer of the contents
of the free-running counter registers to the input capture registers (ICRH1, ICRL1).
Clearing this bit will select the falling edge, setting it selects the rising edge.
8.4.7 IEDG2 - INPUT CAPTURE EDGE SELECT 2
Bit 1 selects which edge of the input capture signal will trigger a transfer of the contents
of the free-running counter registers to the input capture registers (ICRH2, ICRL2).
Clearing this bit will select the falling edge, setting it selects the rising edge.
8.4.8 OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT
Bit 0 selects the output level (high or low) that is clocked into the output compare output
latch at the next successful output compare.
8.5 TIMER STATUS REGISTER (TSR)
Reading the Timer Status Register (TSR) satisfies the first condition required to clear
status flags and interrupts. The only remaining step is to read (or write) the register
associated with the active status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
MOTOROLA
Page 50
Section 8: 16-Bit Timer