MC68HC705MC4 Datasheet, PDF (70/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
9.5.1 PWM DATA REGISTER
The PWMA and PWMB data registers have been mapped to two different addresses: the
Direct address and the Interlock address. The PWMA-D Direct address is $10 and the
PWMA-I Interlock address is $11. The PWMB-D Direct address is $12 and the PWMB-I
Interlock address is $13. A read from either the Direct or the Interlock address will read
the PWM active register. A write to either address will write to the PWM buffer register.
Writing to a PWMx Interlock address will activate a Data - Control interlock mechanism
with the corresponding CTL-x register. Under such a condition, the new value written to
the PWM Interlock data register will not be effective until the end of the current PWM cycle
during which a read or write of the corresponding Control register was executed.
A typical application for such a mechanism is to generate 100% duty cycle when not using
the PWM output mask feature (MEx =0). Synchronized changes to both Data and Control
registers are therefore necessary to avoid PWM glitches. 100% duty cycle can be
generated by clearing PWMx-I, then toggling the state of the POLx bit in the
corresponding CTL-x register. Any new data written to either register will become effective
at the end of the current PWM cycle during which the write or read to CTL-x took place.
Writing to the Direct address will not activate the interlock mechanism with the Control
register. The new value will be updated at the end of the current PWM cycle if the update
bit is clear. The new value will be updated immediately if the update bit is set..
NOTE:
In either case above (write to Interlock or Direct addresses), the interlock
mechanism that interlocks Channel A and Channel B together may
preempt the transfer of the new data to the active registers. See 9.5.3:
OPERATION WITH THE SAME PWM RATES for more detail.
9.5.2 OPERATION WITH DIFFERENT PWM RATES
If RA does not equal RB, channel A and channel B are assumed to be operating
independently of each other and are not interlocked. New data values written to either
PWM channel will occur as discussed in 9.5.1: PWM DATA REGISTER.
Interlocking between the channels only applies when both channels have the same period
(RA = RB). The RATE register is not interlocked with any other registers but it is buffered.
Changes to this register will affect the PWM cycle subsequent to the write. Consequently,
changing the PWM period while generating a PWM signal will not cause erroneous PWM
operation (i.e., glitches). Note that the RATE register is treated as two separate 4-bit
registers, each buffered with the corresponding PWM channel cycle.
NOTE:
Changing the channels from having different periods to having the same
period may cause a phase difference between the channels due to
accumulated clock phase difference. If synchronization is needed
between channel A and channel B, a PRESET cycle must be executed
to provide correct operation of the channel A/B interlock mechanism.
Section 9: Pulse Width Modulator
MOTOROLA
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