MC68HC705MC4 Datasheet, PDF (71/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
9.5.3 OPERATION WITH THE SAME PWM RATES
If RA equals RB, channel A and channel B are assumed to be operating together in a
synchronous fashion and are interlocked. This interlock mechanism described below is in
addition to the buffering and the PWM Data - Control interlock described in 9.5.1: PWM
DATA REGISTER.
A write to either PWMB data register must be followed by a write or a read to either PWMA
data register. Any new data written will become effective at the end of the current PWM
cycle during which the write or read to PWMA took place as shown in Figure 9-8: PWM
Interlock Mechanisms. The interlocking between the data registers is disabled when the
channels have different periods.
A write to CTLB control register must be followed by a write to the CTLA control register.
Any new data written to either register will become effective at the end of the current PWM
cycle during which the write to CTLA took place. The interlocking between the control
registers is disabled when the channels have different periods.
Writing to the PWMx Interlock address will also activate the interlock mechanism with the
CTL-x register as described in 9.5.1: PWM DATA REGISTER. The two interlocking
mechanisms, channel A - channel B and Data - Control, may be in effect at the same time.
Example 1: Writing to PWMB-I ($13) will require a write to CTL-B ($15) to satisfy the Data
- Control interlock. In addition, if RA=RB, the write to either PWMB data register will
require a read/write to either PWMA data register, and the write to CTL-B control register,
will require a write to CTL-A register in order to satisfy the channel A - channel B interlock.
The new contents of all these register will be transferred into their respective active
registers at the end of the current PWM cycle during which all invoked interlock
mechanisms become satisfied if the update bit is clear. If the corresponding update bit is
set, the transfer will occur immediately after the interlock mechanism is satisfied.
Example 2: A write to PWMB-D ($12) will not invoke the Data - Control interlock. However,
if RA=RB, the write to either PWMB data register, will require a read/write to either PWMA
data register to satisfy the channel A - channel B interlock. Note that if a read/write was
made to the PWMA interlock data register, the channel A - channel B interlock would still
be satisfied but the Data - Control interlock will now be invoked for channel A. A write to
CTL-A control register is now necessary to satisfy the channel A Data - Control interlock.
Assuming UPDATEA and UPDATEB are clear in the UPDATE register, the new contents
of all these registers will be transferred into their respective active registers at the end of
the current PWM cycle during which all invoked interlock mechanisms become satisfied.
9.6 PWM DURING WAIT MODE
The PWM continues normal operation during WAIT mode. To decrease power
consumption during WAIT, it is recommended that the PWM subsystem be put into
PRESET state.
MOTOROLA
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Section 9: Pulse Width Modulator