MC68HC705MC4 Datasheet, PDF (15/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
In addition, the IRQ pin may be selected to trigger and interrupt on either the rising or
falling edge of the IRQ pin signal through the EDGE bit in the ISCR.
The MCU completes the current instruction before it responds to the interrupt request.
If the option is selected to include level-sensitive triggering, the IRQ input requires an
external resistor to V_DD for “wire-OR” operation.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise
immunity. See SECTION 4 INTERRUPTS.
This pin is also used to supply the MC68HC705MC4 EPROM array with the programming
voltage.
NOTE: If the voltage level applied to the IRQ pin exceeds V_DD it may affect the
MCU’s mode of operation. See SECTION 2: OPERATING MODES.
1.4 CPU CORE
The MC68HC705MC4 uses a standard P-series CPU core. A description of the P-series
instruction set can be found in MC68HC05P4 Technical Data (Motorola Publication
MC68HC05P4/D).
MOTOROLA
Page 6
Section 1: Introduction