MC68HC705MC4 Datasheet, PDF (60/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
However, a problem can occur when using a timer interrupt function and reading the
free-running counter at random times to, for example, measure an elapsed time. If the
proper precautions are not designed into the application software, a timer interrupt flag
(TOF) could unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set, and
2. The LSB of the free-running counter is read, but not for the purpose of
servicing the flag or interrupt.
The alternate counter registers (ACRH, ACRL) contain the same values as the timer
registers (TMRH, TMRL). Registers ACRH and ACRL can be read at any time without
affecting the Timer Overflow Flag (TOF) or interrupt.
7
6
5
4
3
2
1
0
TSR ^{R ICF2}
ICF1
TOF
OCF
0
0
0
0
$0018 _W
reset ⇒
X
X
X
X
0
0
0
0
Figure 8-12: Timer Status Register (TSR)
8.5.1 ICF2 - INPUT CAPTURE 2 FLAG
Bit 7 is set when the edge specified by IEDG2 in register TCR has been sensed by the
input capture edge detector fed by pin TCAP2. This flag, and the input capture interrupt,
can be cleared by reading register TSR followed by reading the LSB of the input capture
register pair (ICRL2).
8.5.2 ICF1 - INPUT CAPTURE 1 FLAG
Bit 6 is set when the edge specified by IEDG1 in register TCR has been sensed by the
input capture edge detector fed by pin TCAP1. This flag, and the input capture interrupt,
can be cleared by reading register TSR followed by reading the LSB of the input capture
register pair (ICRL1).
8.5.3 TOF - TIMER OVERFLOW FLAG
Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This flag, and
the timer overflow interrupt, can be cleared by reading register TSR followed by reading
the LSB of the timer register pair (TMRL).
8.5.4 OCF - OUTPUT COMPARE FLAG
Bit 4 is set when the contents of the output compare registers match the contents of the
free-running counter. This flag, and the output compare interrupt, can be cleared by
reading register TSR followed by writing the LSB of the output compare register pair
(OCRL).
Section 8: 16-Bit Timer
MOTOROLA
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