MC68HC705MC4 Datasheet, PDF (14/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
1.3.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1
input, with the OSC2 input not connected, as shown in Figure 1-2: Oscillator
Connections (b).
1.3.3 RESET
Driving this input low will reset the MCU to a known start-up state. This pin can also be
pulled low by internal resets. The RESET pin contains an internal Schmitt trigger to
improve its noise immunity. Refer to SECTION 3: RESETS.
1.3.4 PA0, PA1/PWMA1, PA2/PWMB1, PA3/PWMA2, PA4/PWMB2, PA5/PWMA3,
PA6/PWMB3, PA7
These eight I/O pins comprise Port A and are shared with the PWM subsystem. The state
of any pin is software programmable and all Port A lines are configured as inputs during
power-on or reset. All Port A pins have high source current capability to simplify
interfacing to external devices, such as small triacs. Refer to SECTION 6:
INPUT/OUTPUT PORTS and SECTION 9: PULSE WIDTH MODULATOR.
1.3.5 PB4/TDO, PB5/RDI, PB6, PB7
These four I/O pins comprise Port B. Two pins are shared with the SCI communication
subsystem. The state of any pin is software programmable and all Port B lines are
configured as inputs during power-on or reset. Refer to SECTION 6: INPUT/OUTPUT
PORTS and SECTION 10: SERIAL COMMUNICATIONS INTERFACE.
1.3.6 PC0:5/AD0:5, PC6/V_REFH, PC7/V_REFL
These eight I/O pins comprise Port C and are shared with the A/D Converter subsystem.
The state of any pin is software programmable and all Port C lines are configured as
inputs during power-on or reset. Refer to SECTION 6: INPUT/OUTPUT PORTS and
SECTION 7: ANALOG SUBSYSTEM.
1.3.7 PD6/TCAP1/TCMP, PD7/TCAP2
These two I/O pins comprise Port D and are shared with the 16-bit timer subsystem. PD7
is always an input. PD6 can be used as an input or output port if the TCAP1 interrupt is
disabled and the TCAP1/TCMP bit is clear in the TCR. This is the state upon RESET.
Writes to PD7 have no effect. They may be read at any time, regardless of the mode of
operation of the 16-bit timer. Refer to SECTION 6: INPUT/OUTPUT PORTS and
SECTION 8: 16-BIT TIMER.
1.3.8 IRQ (MASKABLE INTERRUPT REQUEST) / V_PP
This pin has two different choices of interrupt triggering sensitivity through the IRQ bit in
the Interrupt Status and Control Register (ISCR). The choices are:
• edge-sensitive triggering only.
• both edge-sensitive and level-sensitive triggering.
Section 1: Introduction
MOTOROLA
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