MC68HC705MC4 Datasheet, PDF (31/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
4.2 SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is
executed regardless of the state of the I-bit in the CCR. As with any instruction, interrupts
pending during the previous instruction will be serviced before the SWI opcode is fetched.
The interrupt service routine address for the SWI instruction is specified by the contents
of memory locations $0FFC and $0FFD.
4.3 HARDWARE INTERRUPTS
All hardware interrupts are maskable by the I-bit in the CCR. If the I-bit is set, all hardware
interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware
interrupts. There are four hardware interrupts that are explained in the following sections.
4.3.1 EXTERNAL INTERRUPT (IRQ)
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and
external) are disabled. Clearing the I-bit enables interrupts (subject to their individual
interrupt enable control flag status). IRQ now has an independent interrupt mask bit in the
Interrupt Status and Control Register (ISCR) that must also be cleared to enable its
corresponding interrupt.
The interrupt mask bit operates by inhibiting the interrupt signal after the appropriate
interrupt request latch. This feature allows the interrupt to be recognized and latched even
if the mask is set.
When the IRQ input goes to the active level for at least one t_ILIH, a logic one is latched
internally to signify an interrupt has been requested. When the MCU completes its current
instruction, the interrupt latch is tested. If the interrupt latch contains a logic one, and the
interrupt mask bit (I-bit) in the condition code register and the IRQ mask bit (IRQM) in the
ISCR are both clear, then the MCU can begin the interrupt sequence. The state of the
interrupt latch is reflected in the interrupt request bit (REQ) in the ISCR, and is
automatically cleared during interrupt processing. See Figure 4-2: Interrupt Status and
Control Register.
IRQ interrupt requests are automatically acknowledged and cleared during interrupt
processing. It may also be cleared through software by setting the acknowledge bit in the
ISCR. Setting this bit is a “one-shot” operation and will not affect subsequent interrupt
operation. The action of clearing the acknowledge bit will clear the request bit. This allows
the programmer the option to cancel spurious interrupts that occur while the interrupt
mask bits are set. This may be necessary in systems where it is desirable to prevent
redundant (ghost) entries to the interrupt service routine (where the interrupt mask is
eventually cleared).
MOTOROLA
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Section 4: Interrupts