MC68HC705MC4 Datasheet, PDF (86/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
RIE bit in SCCR2 is also set. Clear the RDRF bit by reading the SCSR with
RDRF set, and then reading the SCDR. Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle
This clearable, read-only bit is set when 10 or 11 consecutive logic ones
appear on the receiver input. IDLE generates an interrupt request if the ILIE bit
in SCCR2 is also set. Clear the IDLE bit by reading the SCSR with IDLE set,
and then reading the SCDR. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun
This clearable, read-only bit is set if the SCDR is not read before the receive
shift register receives the next word. OR generates an interrupt request if the
RIE bit in SCCR2 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading the SCSR with
OR set, and then reading the SCRD. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data received in
the SCI data register. Clear the NF bit by reading the SCSR, and then reading
the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error
This clearable, read-only flag is set when there is a logic zero where a stop bit
should be in the character shifted into the receive shift register. If the received
word causes both a framing error and an overrun error, the OR bit is set and
the FE bit is not set. Clear the FE bit by reading the SCSR, and then reading
the SCDR. Reset clears the FE bit.
1 = Framing error
0 = No framing error
Section 10: Serial Communications Interface
MOTOROLA
Page 77