MC68HC705MC4 Datasheet, PDF(49/99 Page) Motorola, Inc

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MC68HC705MC4 Datasheet, PDF (49/99 Pages) Motorola, Inc – Microcontrollers　

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MC68HC705MC4 Specification Rev. 1.5

7.3.2 MULTI-CHANNEL OPERATION

In User Mode, a multiplexer allows the single A/D converter to select one of eight analog

signals, two of which are VREFH and VREFL. The eight pins of Port C are input signals to the

multiplexer.

7.3.3 UNUSED A/D INPUTS AS I/O

When the A/D system is enabled, two pins, VREFH (PC6) and VREFL(PC7), are automatically

assumed to have their dedicated functions. The Channel Select Bits define which Port C

pin will be used as the analog in pin and overrides any control from the Port C I/O logic by

forcing that pin as the input to the analog circuitry. The Port C pins that are not selected

by the Channel Select Bits, [CH3:0], are controlled by the Port C I/O logic, and thus can

be used as general purpose I/O. Writes to Port C will not have any effect on the selected

channel.

NOTE:

The DDR bits corresponding to an A/D channel used by the application

must be cleared. For example, AD2 shares a pin with PC2, so the

DDRC2 bit must be cleared (unless this is the only channel the A/D ever

selects). This is to ensure that the port output value held in the Port C

data register is not driven out of the pin when the A/D has selected

another channel for conversion.

7.4 A/D STATUS AND CONTROL REGISTER (ADSCR) $25

The following paragraphs describe the function of the A/D Status and Control Register.

R COCO

ADSR

ADRC

ADON

CH3

CH2

CH1

CH0

$0025 W

reset â

Figure 7-1: A/D Status and Control Register

7.4.1 COCO - CONVERSIONS COMPLETE

This read-only status bit is set when a conversion is completed, indicating that the A/D

Data Register contains valid results. This bit is cleared whenever the A/D Status and

Control Register is written and a new conversion is automatically started, or whenever the

A/D Data Register is read. Once a conversion has been started by writing to the A/D

Status and Control Register, conversions of the selected channel will continue every 32

cycles until the A/D Status and Control Register is written again. In this continuous

conversion mode, the A/D Data Register will be filled with new data, and the COCO bit

set, every 32 cycles. Data from the previous conversion will be overwritten regardless of

the state of the COCO bit prior to writing.

MOTOROLA

Page 40

Section 7: Analog Subsystem

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