MC68HC705MC4 Datasheet, PDF (21/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
2.2.2.1 LATCH - EPROM Latch Control
The LATCH bit is a read/write bit. When set, the address and data buses are latched when
a write to EPROM is done. EPROM cannot be read if LATCH = 1.
1 = EPROM address and data bus configured for programming.
0 = EPROM address and data bus configured for normal reads.
2.2.2.2 EPGM - EPROM Program Control
The EPGM bit may be read or cleared at any time. It may only be set if LATCH=1. If
LATCH=0, the EPGM is automatically cleared. LATCH and EPGM cannot both be set on
the same write.
1 = Programming power switched on to the EPROM array.
0 = Programming power switched off the EPROM array.
2.2.3 MASK OPTION REGISTER (MOR) $0F00
This register is latched upon RESET and at regular intervals as determined by COP
timeout period. It is an EPROM byte located at $0F00 and holds the option bit for COP
disable/enable.
7
6
5
4
3
2
1
0
R
U
U
U
U
U
U
U
COPE
MOR
$0F00 _W
COPE
reset ⇒
0
0
0
0
0
0
0
0
U = Undetermined
UNIMPLEMENTED
Figure 2-6: Mask Option Register
2.2.3.1 COP - COP enable/disable
1 = The COP is enabled.
0 = (erased state) The COP is disabled.
MOTOROLA
Page 12
Section 2: Operating Modes