MC68HC705MC4 Datasheet, PDF (80/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
INTERNAL DATA BUS
16X
BAUD RATE
16
CLOCK
PIN BUFFER
AND CONTROL
DATA
RECOVERY
SCDR ($000E)
RECEIVE SHIFT REGISTER
876543210
DDR
NF
SCI
INTERRUPT
REQUEST
FE
R8
RE
M
SCI
TRANSMIT
REQUESTS
RDRF
RIE
OR
RIE
IDLE
ILIE
WAKEUP
LOGIC
7
BAUD RATE REGISTER (BAUD)
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
T8
TCIE
TC
BIT 6
5
SCP1
RIE
RDRF
BIT 5
4
3
2
SCP0
SCR2
M WAKE
ILIE TE RE
IDLR OR NF
BIT 4 BIT 3 BIT 2
RWU
1
0
SCR1 SCR0 $000A
$000B
RWU SBK $000C
FE
0 $000D
BIT 1 BIT 0 $000E
Figure 10-3: SCI Receiver
10.4.2.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI
control register 1 (SCCR1) determines character length. When receiving 9-bit date, bit R8
in SCCR1 is the ninth bit (bit 8).
10.4.2.2 Character Reception
During reception, the receive shift register shifts characters in from the PB5/RDI pin. The
SCI data register (SCDR) is the read-only buffer between the internal data bus and the
receive shift register.
Section 10: Serial Communications Interface
MOTOROLA
Page 71