MC68HC705MC4 Datasheet, PDF (67/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
selected channel will output the PWM waveform. See Figure 9-6: PWM Output MUX
Logic and Figure 9-7: PWM Control Example.
If MEx is clear and all CSx bits are clear, it also disables the corresponding 8-bit counter
to save power. If both counters are disabled, the clock generator will also be disabled.
PORT DATA REGISTER
ME^. CS^. DDR
PWM OUTPUT
CS
MSK
PORT
OUTPUT
LOGIC
ME^. CS
Figure 9-6: PWM Output MUX Logic
9.2.5 MSKx[3:1] - MASK
Set mask values for channels that are not selected by CSx when MEx is set. A Mask value
of 1 drives unselected mux-pins high. A Mask value of 0 drives unselected mux-pins low.
When MEx is clear, the Mask bits have no effect.
If the mask feature is enabled (MEx =1), the mask bits also provide an alternative method
of generating 0% or 100% values. The conventional method generates 100% duty cycle
by inverting the output polarity and simultaneously clearing the PWM Data bits.
See Figure 9-6: PWM Output MUX Logic and Figure 9-7: PWM Control Example.
9.2.6 UPDATEx
The UPDATEA and UPDATEB bits control when the registers for PWM A and PWM B will
be updated. If the corresponding bit is clear, the registers will be updated at the end of the
current cycle. If the corresponding bit is set, the registers will be updated immediately. The
normal interlock restrictions still apply.
MOTOROLA
Page 58
Section 9: Pulse Width Modulator