MC68HC705MC4 Datasheet, PDF (52/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
SECTION 8
16-BIT TIMER
The MC68HC705MC4 MCU contains a single 16-bit programmable timer with two Input
Capture functions and an Output Compare function. The 16-bit timer is driven by the
output of a fixed divide-by-four prescaler operating from the internal clock. The 16-bit
timer may be used for many applications including input waveform measurement while
simultaneously generating an output waveform. Pulse widths can vary from microseconds
to seconds depending on the oscillator frequency selected. The 16-bit timer is also
capable of generating periodic interrupts. See Figure 8-1: 16-Bit Timer Block Diagram.
Because the timer has a 16-bit architecture, each function is represented by two registers.
Each register pair contains the high and low byte of that function. Generally, accessing
the low byte of a specific timer function allows full control of that function; however, an
access of the high byte inhibits that specific timer function until the low byte is also
accessed.
NOTE:
The I-bit in the Condition Code Register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time that
the high and low bytes are accessed.
8.1 TIMER
The key element of the programmable timer is a 16-bit free-running counter, or Timer
Registers, preceded by a prescaler which divides the internal clock by four. The prescaler
gives the timer a resolution of 1.33 microseconds when a 3 MHz crystal is used. The
counter is incremented to increasing values during the low portion of the internal clock
cycle.
The double byte free-running counter can be read from either of two locations: the Timer
Registers (TMRH, TMRL) or the Alternate Counter Registers (ACRH, ACRL). Both
locations will contain identical values. A read sequence containing only a read of the LSB
of the counter (TMRL / ACRL) will return the count value at the time of the read. If a read
of the counter accesses the MSB first (TMRH / ACRH) it causes the LSB (TMRL / ACRL)
to be transferred to a buffer. This buffer value remains fixed after the first MSB byte read
even if the MSB is read several times. The buffer is accessed when reading the counter
LSB (TMRL / ACRL), and thus completes a read sequence of the total counter value.
When reading either the Timer or Alternate Counter registers, if the MSB is read, the LSB
must also be read to complete the read sequence. See Figure 8-2: Timer Registers
(TMRH / TMRL) and Figure 8-3: Alternate Counter Registers (ACRH / ACRL).
Section 8: 16-Bit Timer
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