MC68HC705MC4 Datasheet, PDF (28/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
SECTION 4
INTERRUPTS
The MCU can be interrupted eight different ways:
1. Nonmaskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. Input Capture Interrupt (TIMER)
4. Output Compare Interrupt (TIMER)
5. Timer Overflow Interrupt (TIMER)
6. Serial Communications Interrupt (SCI)
7. Core Timer Overflow Interrupt (CTIMER)
8. Real Time Interrupt (CTIMER)
Interrupts cause the processor to save the register contents on the stack and to set the
interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts
do not cause the current instruction execution to be halted, but are considered pending
until the current instruction is completed.
When the current instruction is completed, the processor checks all pending hardware
interrupts. If interrupts are not masked (I-bit in the Condition Code Register is clear), and
the corresponding interrupt enable bit is set, the processor proceeds with interrupt
processing. Otherwise, the next instruction is fetched and executed. The SWI is executed
the same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents on the stack,
sets the I-bit in the CCR, and fetches the address of the corresponding interrupt service
routine from the vector table at locations $0FF0 thru $0FFF. If more than one interrupt is
pending when the interrupt vector is fetched, the interrupt with the highest vector location
shown in Table 4-1: Vector Addresses for Interrupts and Reset will be serviced first.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the CPU state to be recovered from the stack and
normal processing to resume at the next instruction that was to be executed when the
interrupt took place. Figure 4-1: Interrupt Processing Flowchart shows the sequence
of events that occur during interrupt processing.
The interrupts fall into three categories: reset, software, and hardware.
Section 4: Interrupts
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