MC68HC705MC4 Datasheet, PDF (32/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
Note that the IRQM is cleared (enabled) during reset, although no interrupts can occur
until the interrupt mask bit of the CCR is cleared. It is set during reset. The interrupt
request latches are also cleared during reset.
7
6
5
4
3
2
1
0
R
0
REQ
0
0
0
ISCR
IRQM
IRQS
EDGE
$000F _W
ACK
reset ⇒
0
0
0
0
0
0
0
0
Figure 4-2: Interrupt Status and Control Register
4.3.1.1 IRQM - IRQ Enable Mask
The IRQM bit is a read/write bit that will disable the IRQ interrupt when set. IRQM is
cleared by reset.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
4.3.1.2 IRQS - IRQ Sensitivity
The IRQS bit is a read/write bit that will select whether the IRQ interrupt is edge-sensitive
only or both edge-sensitive and level-sensitive. IRQS is cleared by reset.
1 = both edge-sensitive and level-sensitive
0 = edge-sensitive only
4.3.1.3 EDGE - IRQ Active Edge Select
The EDGE bit is a read/write bit that allows the user to select which edge, rising or falling,
of the signal at the IRQ pin will generate an interrupt. Both rising and falling edge
sensitivity may be achieved in software by toggling the EDGE bit from within the IRQ
service routine. EDGE is cleared by reset.
1 = Rising edge IRQ interrupt
0 = Falling edge IRQ interrupt
4.3.1.4 REQ - IRQ Interrupt Request
The REQ bit is a read-only bit. The IRQ interrupt request bit and latch are cleared during
IRQ exception processing. Therefore, one external IRQ interrupt pulse can be latched and
subsequently serviced as soon as the I-bit is cleared. REQ will be cleared by reset.
1 = IRQ interrupt request pending
0 = No IRQ interrupt request pending
4.3.1.5 ACK - IRQ Interrupt Request Acknowledge
This bit is write only - it will always read as a zero. Writing a one to this bit will acknowledge
the interrupt by clearing the corresponding interrupt request bit.
Section 4: Interrupts
MOTOROLA
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