MC68HC705MC4 Datasheet, PDF (55/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
8.2 OUTPUT COMPARE
The Output Compare function may be used to generate an output waveform and/or as an
elapsed time indicator. If the TCMP/TCAP1 bit of the TCR is set, output to the port pin is
enabled. All of the bits in the Output Compare register pair OCRH / OCRL are readable
and writable and are not altered by the 16-bit timer’s control logic. Reset does not affect
the contents of these registers. See Figure 8-5: Output Compare Registers (OCRH /
OCRL).
7
6
5
4
3
2
1
0
R
OCRH
$001D _W
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
R
OCRL
$001E _W
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
reset ⇒
X
X
X
X
X
X
X
X
Figure 8-5: Output Compare Registers (OCRH / OCRL)
The contents of the output compare registers are compared with the contents of the
free-running counter once every four internal clock cycles. If a match is found, the Output
Compare Flag bit (OCF) is set and the Output Level bit (OLVL) is clocked to the output
latch. The values in the output compare registers and output level bit should be changed
after each successful comparison to control an output waveform, or to establish a new
elapsed time-out. An interrupt can also accompany a successful output compare if the
Output Compare Interrupt Enable bit (OCIE) is set.
After a CPU write cycle to the MSB of the output compare register pair (OCRH), the output
compare function is inhibited until the LSB (OCRL) is written. Both bytes must be written
if the MSB is written. A write made only to the LSB will not inhibit the compare function.
The free-running counter increments every four internal clock cycles. The minimum time
required to update the output compare registers is a function of software rather than
hardware.
The output compare Output Level bit (OLVL) will be clocked to its output latch regardless
of the state of the Output Compare Flag bit (OCF). A valid output compare must occur
before the OLVL bit is clocked to its output latch (TCMP).
NOTE: The TCMP/TCAP1 bit of the TCR only affects the output of the latch to
the port pin and has no effect on other parts of the Output Compare
function.
Since neither the Output Compare Flag (OCF) nor the output compare registers are
affected by reset, care must be exercised when initializing the output compare function.
The following procedure is recommended:
1. Block interrupts by setting the I-bit in the Condition Code Register
(CCR).
MOTOROLA
Page 46
Section 8: 16-Bit Timer