MC68HC705MC4 Datasheet, PDF (78/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
INTERNAL DATA BUS
SCDR ($000E)
1X
BAUD RATE
CLOCK
TRANSMIT SHIFT REGISTER
H8 7 6 5 4 3 2 1 0 L
M
T8
PIN BUFFER
AND CONTROL
PD2/
MISO
DDR1
SBK
TRANSMITTER
CONTROL LOGIC
TE
TDRE
TIE
TC
TCIE
SCI
RECEIVE
REQUESTS
SCI
INTERRUPT
REQUEST
7
BAUD RATE REGISTER (BAUD)
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
T8
TCIE
TC
BIT 6
5
SCP1
RIE
RDRF
BIT 5
4
3
2
SCP0
SCR2
M WAKE
ILIE TE RE
IDLR OR NF
BIT 4 BIT 3 BIT 2
1
SCR1
RWU
FE
BIT 1
0
SCR0 $000A
$000B
SBK $000C
0 $000D
BIT 0 $000E
Figure 10-2: SCI Transmitter
Writing a logic one to the TE bit in SCI control register 2 (SCCR2), and then writing data
to the SCDR, begins the transmission. At the start of a transmission, transmitter control
logic automatically loads the transmit shift register with a preamble of logic ones. After the
preamble shifts out, the control logic transfers the SCDR data into the shift register. A logic
zero start bit automatically goes into the least significant bit position of the shift register,
and a logic one stop bit goes into the most significant bit position.
When the data in the SCDR transfers to the transmit shift register, the transmit data
register empty (TDRE) flag in the SCI status register (SCSR) becomes set. The TDRE flag
indicates that the SCDR can accept new data from the internal data bus.
Section 10: Serial Communications Interface
MOTOROLA
Page 69