MC68HC705MC4 Datasheet, PDF (63/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
9.1 PWM REGISTERS
R
CTL-A
MEA
$0014 _W
POLA
R
CTL-B
MEB
$0015 _W
POLB
R
RATE
RA3
RA2
$0016 _W
R
UPDATE _UPDATEA
$0027 _W
reset ⇒
0
UPDATEB
0
MSKA3
MSKB3
RA1
0
MSKA2
MSKB2
RA0
0
MSKA1
MSKB1
RB3
0
CSA3
CSB3
RB2
0
CSA2
CSB2
RB1
0
CSA1
CSB1
RB0
0
Figure 9-2: PWM CTL Registers
R
PWMA-D
$0010 _W
PWMA7
R
PWMA-I
$0011 _W
PWMA7
R
PWMB-D
$0012 _W
PWMB7
R
PWMB-I
$0013 _W
PWMB7
reset ⇒
X
PWMA6
PWMA6
PWMB6
PWMB6
X
PWMA5
PWMA5
PWMB5
PWMB5
X
PWMA4
PWMA4
PWMB4
PWMB4
X
PWMA3
PWMA3
PWMB3
PWMB3
X
PWMA2
PWMA2
PWMB2
PWMB2
X
PWMA1
PWMA1
PWMB1
PWMB1
X
PWMA0
PWMA0
PWMB0
PWMB0
X
Figure 9-3: PWMA & PWMB Data Registers
The PWM subsystem control and data registers are all buffered, as shown in Figure 9-10:
PWM Register Structure. Each register consists of an active register, which contains the
data used by the PWM subsystem, and a buffer register, which contains the data most
recently written to the register address. Writes to the buffer registers are transferred to the
active registers at the end of the PWM period if the respective bit in the UPDATE register
is set to zero. If it is set to one, the transfer will occur immediately. In addition, a predefined
sequence of register accesses may also need to be completed before the new contents
MOTOROLA
Page 54
Section 9: Pulse Width Modulator