MC68HC705MC4 Datasheet, PDF (51/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
Table 7-1: A/D Channel Assignments
CHANNEL
0
1
2
SIGNAL
AD0 PORT C BIT 0
AD1 PORT C BIT 1
AD2 PORT C BIT 2
3
AD3 PORT C BIT 3
4
AD4 PORT C BIT 4
5
AD5 PORT C BIT 5
6
UNUSED
7
UNUSED
8
V_REFH
9
V_REFL
a
(V_REFH + V_REFL)/2
b-f
V_REFL
7.5 A/D DATA REGISTER ($24)
One 8-bit result register is provided. This register is updated each time COCO is set.
Reset has no effect on this register.
ADDR
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
$24
Figure 7-2: A/D Data Register
7.6 A/D DURING WAIT MODE
The A/D continues normal operation during WAIT mode. To decrease power consumption
during WAIT, it is recommended that both the ADON and ADRC bits in the A/D Status and
Control Register be cleared if the A/D converter is not being used. If the A/D converter is
in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit
be cleared.
7.7 A/D DURING STOP MODE
In STOP mode, the comparator and charge pump are turned off and the A/D ceases to
function. Any pending conversion is aborted. When the clocks begin oscillation upon
leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize
enough to provide conversions to the specified accuracy. Normally, the delays built into
the MC68HC705MC4 when coming out of STOP mode are sufficient for this purpose,
therefore no explicit delays need to be built into the software.
MOTOROLA
Page 42
Section 7: Analog Subsystem