MC68HC705MC4 Datasheet, PDF (43/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
(i.e., not line peak values). Care should be taken to ensure parasitic series resistor and
PCB capacitance will not couple transients to the MCU input.
PA7 has been intentionally located between V_DD and V_SS to provide a lowest possible
impedance path for the injected currents, in particular fast transients. Although any I/O
port will function in this manner, it is recommended that only PA7 be used for such an
interface.
L
LINE
N
R
PA7
MCU
V_SS
Figure 6-2: Line Interface Circuitry
6.2 PORT B
Port B is a 4-bit bidirectional port that can share pins PB4-PB5 with the SCI subsystem.
The Port B data register is located at address $0001 and its Data Direction Register
(DDR) is located at address $0005. Reset does not affect the data registers, but clears
the DDRs, thereby setting all of the port pins to input mode. Writing a one to a DDR bit
sets the corresponding port pin to output mode.
PB7 features a larger n-channel output device and can therefore sink more current than
a standard port. (Refer to SECTION 12: ELECTRICAL SPECIFICATIONS.)
PB4-PB5 may be used for general I/O applications when the SCI subsystem is disabled.
When the SCI subsystem is enabled, Port B registers are still accessible to software.
MOTOROLA
Page 34
Section 6: Input/Output Ports