MC68HC705MC4 Datasheet, PDF (91/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
As seen in Figure 11-1: Core Timer Block Diagram, the Core Timer is driven by the
internal bus clock divided by four as a fixed prescaler. This signal drives an 8-bit ripple
counter. The value of this 8-bit ripple counter can be read by the CPU at any time by
accessing the Ctimer Counter Register (CTCR) at address $09. A timer overflow function
is implemented on the last stage of this counter, giving a possible interrupt at the rate of
E/1024. Two additional stages produce the POR function at E/4064. The Timer Counter
Bypass circuitry (available only in Test Mode) is at this point in the timer chain. This circuit
is followed by one more stage, with the resulting clock (E/8192) driving the Real Time
Interrupt circuit. The RTI circuit consists of four divider stages with a 1 of 4 selector. The
output of the RTI circuit is further divided by eight to drive the mask optional COP
Watchdog Timer circuit. The RTI rate selector bits, and the RTI and CTOF enable bits and
flags are located in the Ctimer Control and Status Register(CTCSR) at location $08.
11.1 CTIMER CONTROL AND STATUS REGISTER (CTCSR) $08
The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real
time interrupt rate select bits. Figure 11-2: Core Timer Control and Status Register
(CTCSR) shows the value of each bit in the CTCSR when coming out of reset.
$08 CTOF RTIF CTOIE RTIE
--
--
RT1
RT0
RESET: 0
0
0
0
0
0
1
1
Figure 11-2: Core Timer Control and Status Register (CTCSR)
11.1.1 CTOF - Core Timer Overflow Flag
CTOF is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over
from $FF to $00. A CPU interrupt request will be generated if CTOIE is set. Clearing the
CTOF is done by writing a ‘0’ to it. Writing a ‘1’ to CTOF has no effect on the bit’s value.
Reset clears CTOF.
11.1.2 RTIF - Real Time Interrupt Flag
The Real Time Interrupt circuit consists of a four stage divider and a 1 of 4 selector. The
clock frequency that drives the RTI circuit is E/2¹³ (or E/8192) with four additional divider
stages giving a maximum interrupt period of 4 seconds at a crystal frequency of 32.768
kHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (1
of 4 selection) stage goes active. A CPU interrupt request will be generated if RTIE is set.
Clearing the RTIF is done by writing a ‘0’ to it. Writing a ’1’ to RTIF has no effect on this
bit. Reset clears RTIF.
11.1.3 CTOIE - Core Timer Overflow Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset
clears this bit.
11.1.4 RTIE - Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset
clears this bit.
MOTOROLA
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Section 11: Core Timer