MC68HC705MC4 Datasheet, PDF (45/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
6.4 PORT D
Port D is a 2-bit port. PD7 and PD6 are shared with the 16-bit timer. PD6 is a bi-directional
I/O pin but PD7 is an input only pin. The Port D data register is located at address $0003
and its Data Direction Register (DDR) is located at address $0007. Reset clears the DDR
setting PD6 to an input but does not affect the data registers.
PD6 may be used for general I/O applications when the SCI subsystem is disabled. PD7
may be used as a general purpose input when the SCI subsystem is disabled. When the
SCI subsystem is enabled, Port D registers are still accessible to software. Writing to
either of the Port D registers with the timer enabled could interfere with timer operation.
See SECTION 8: 16-BIT TIMER for a discussion of the timer subsystem.
Read $0007
TCMP/TCAP1
TCMP
Reset
(RST)
Read $0003
Internal HC05
Data Bus
Data Direction
Register Bit
Data
Register Bit
I/O
Output
Pin
Figure 6-5: Port D Circuitry
6.5 I/O PORT PROGRAMMING
Each pin on Ports A-C may be programmed as an input or an output under software
control as shown in Table 6-1: Port A I/O Pin Functions, Table 6-2: Port B I/O Pin
Functions, Table 6-3: Port C I/O Pin Functions, and Table 6-4: Port D I/O Pin
Functions. The direction of a pin is determined by the state of its corresponding bit in the
associated port Data Direction Register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic one. A pin is configured as an input if its
corresponding DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, which configures all Port pins as inputs. The
DDRs are capable of being written to or read by the processor. During the programmed
output state, a read of the data register will actually read the value of the output data latch
and not the level on the I/O port pin.
MOTOROLA
Page 36
Section 6: Input/Output Ports