MC68HC705MC4 Datasheet, PDF (27/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
3.2.2 POWER-ON RESET (POR)
An internal reset is generated on power-up to allow the internal clock generator to
stabilize. The power-on reset is strictly for power turn-on conditions and should not be
used to detect a drop in the power supply voltage. There is a 4064 internal processor clock
cycle (t_CYC) oscillator stabilization delay after the oscillator becomes active. If the RESET
pin is active at the end of this 4064 cycle delay, the MCU will remain in the reset condition
until RESET goes inactive.
The POR will generate the RST signal and reset the MCU. If any other reset function is
active at the end of this 4064 internal clock cycle delay, the RST signal will remain active
until the other reset condition(s) end.
3.2.3 COMPUTER OPERATING PROPERLY (COP) RESET
When the COP watchdog timer is enabled (by Mask Option) the internal COP reset is
generated automatically by a time-out of the COP watchdog timer. This timer is
implemented as part of the Core Timer. See SECTION 11: CORE TIMER. The COP
watchdog counter is cleared by writing a logical zero to bit zero at location $0FF0.
The COP watchdog timer can be disabled by Mask Option or by applying 2 × V_DD to the
IRQ pin at the rising edge of RESET (e.g. during Self-Check operation). When the IRQ
pin is returned to its normal operating voltage range (between V_SS - V_DD) at the rising edge
of RESET, the COP watchdog timer’s output will be restored if the COP Mask Option is
enabled.
The COP register is shared with the MSB of the Core Timer Interrupt Vector as shown in
Figure 3-2: COP Watchdog Timer Register. Reading this location will return the MSB
of the Core Timer Interrupt Vector. Writing to this location will clear the COP watchdog
timer.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
COPR
$0FF0 _W
COPR
reset ⇒
0
0
0
0
0
0
0
0
UNIMPLEMENTED
Figure 3-2: COP Watchdog Timer Register
MOTOROLA
Page 18
Section 3: Resets