MC68HC705MC4 Datasheet, PDF (33/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
NOTE: The use of separate request and acknowledge bits allows the safe use
of read-modify-write instructions (for example, BSET, BCLR) on the
ISCR register.
IRQS
IRQ
Edge- and Level-Sensitive
ACK
Clear
V_DD
D
Q
REQ
INTERRUPT
EDGE
IRQM
Figure 4-3: Interrupt Hardware Structure
NOTE:
When the Edge- and Level-Sensitive Mask Option is selected, the
voltage applied to the IRQ pin must return to the inactive state before the
RTI instruction in the interrupt service routine is executed. If the IRQ pin
remains in at the active level, the interrupt service routine will be
re-entered after the RTI is executed. Setting the ACK bit will have no
effect under these circumstances.
4.3.2 TIMER INTERRUPTS
4.3.2.1 INPUT CAPTURE INTERRUPTS
The input capture interrupts are generated by the 16-bit timer as described in SECTION
8: 16-BIT TIMER. The input capture interrupt flags are located in register TSR and the
corresponding enable bits can be found in register TCR. The I-bit in the CCR must be
clear in order for either input capture interrupt to be enabled. The interrupt service routine
MOTOROLA
Page 24
Section 4: Interrupts