MC68HC705MC4 Datasheet, PDF (30/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
From RESET
Y
Is I-bit
Set?
N
IRQ
Y
interrupt?
N
Timer
Y
interrupt?
N
SCI
Y
interrupt?
N
Core Timer
Y
interrupt?
N
Fetch Next Instruction
SWI
Y
instruction?
N
RTI
Y
instruction?
N
Execute Instruction
Clear IRQ
Request
Latch
Stack
PC, X, A, CC
Set
I-bit in CCR
Load PC From:
SWI: $0FFC, $0FFD
IRQ: $0FFA-$0FFB
TMR IC2: $0FF8-$0FF9
TMR IC1:$0FF6-$0FF7
TMR OC/OF:$0FF4-$0FF5
SCI: $0FF2-$0FF3
CTMR: $0FF0-$0FF1
Restore Resistors
from stack
CC, A, X, PC
Figure 4-1: Interrupt Processing Flowchart
4.1 RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted upon in
a similar manner as shown in Figure 4-1: Interrupt Processing Flowchart. A low level
input on the RESET pin or internally generated RST signal causes the program to vector
to its starting address which is specified by the contents of memory locations $0FFE and
$0FFF. The I-bit in the condition code register is also set. The MCU is configured to a
known state during this type of reset, as previously described in SECTION 3: RESETS.
Section 4: Interrupts
MOTOROLA
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