MC9S12C128V1 Datasheet, PDF (96/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.4.7 Port P Interrupt Enable Register (PIEP)
Module Base + 0x001E
R
W
Reset
7
PIEP7
0
Read: Anytime.
Write: Anytime.
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Table 2-26. PIEP Field Descriptions
1
PIEP1
0
0
PIEP0
0
Field
Description
7–0
PIEP[7:0]
Pull Select Port P — This register disables or enables on a per pin basis the edge sensitive external interrupt
associated with port P.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
2.3.2.4.8 Port P Interrupt Flag Register (PIFP)
Module Base + 0x001F
R
W
Reset
7
PIFP7
0
Read: Anytime.
Write: Anytime.
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
0
0
0
0
0
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Table 2-27. PIFP Field Descriptions
1
PIFP1
0
0
PIFP0
0
Field
Description
7–0
PIFP[7:0]
Interrupt Flags Port P — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSP register. To clear this flag, write a “1” to the corresponding bit
in the PIFP register. Writing a “0” has no effect.
0 No active edge pending.
Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
96
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24