MC9S12C128V1 Datasheet, PDF (487/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 17 16 Kbyte Flash Module (S12FTS16KV1)
then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 17-21.
For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits
FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As
a result, the Flash algorithm timings are increased over optimum target by:
(200 – 190) ⁄ 200 × 100 = 5%
Command execution time will increase proportionally with the period of FCLK.
CAUTION
Because of the impact of clock synchronization on the accuracy of the
functional timings, programming or erasing the Flash array cannot be
performed if the bus clock runs at less than 1 MHz. Programming or erasing
the Flash array with an input clock < 150 kHz should be avoided. Setting
FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array
due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus)
< 5µs can result in incomplete programming or erasure of the Flash array
cells.
If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written
to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag
in the FSTAT register will set.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
487
Rev 01.24