MC9S12C128V1 Datasheet, PDF (675/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Appendix A Electrical Characteristics
In Table A-21 the timing characteristics for master mode are listed.
Table A-21. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
P SCK Frequency
P SCK Period
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid after SCK Edge
D Data Valid after SS fall (CPHA=0)
D Data Hold Time (Outputs)
D Rise and Fall Time Inputs
D Rise and Fall Time Outputs
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
20
—
t_rfi
—
—
t_rfo
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
A.6.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT) ¹⁰
7
MISO
(OUTPUT)
MOSI
(INPUT)
NOTE: Not defined!
1
12
13 3
2
4
4
12
13
see
note
SLAVE MSB
5
6
MSB IN
9
BIT 6 . . . 1
BIT 6 . . . 1
11
11
SLAVE LSB OUT
LSB IN
Figure A-8. SPI Slave Timing (CPHA=0)
8
SEE
NOTE
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
675
Rev 01.24