MC9S12C128V1 Datasheet, PDF (231/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.3.2.3 ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt, and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Module Base + 0x0002
R
W
Reset
7
ADPU
0
6
AFFC
5
AWAI
4
ETRIGLE
3
ETRIGP
2
ETRIGE
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-5. ATD Control Register 2 (ATDCTL2)
1
ASCIE
0
0
ASCIF
0
Read: Anytime
Write: Anytime
Table 8-1. ATDCTL2 Field Descriptions
Field
7
ADPU
6
AFFC
5
AWAI
4
ETRIGLE
3
ETRIGP
2
ETRIGE
Description
ATD Power Down — This bit provides on/off control over the ATD10B8C block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
clear the associate CCF flag).
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause
the associate CCF flag to clear automatically.
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B8C
block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD
requires a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this
conversion should be ignored.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 8-2 for details.
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 8-2 for details.
External Trigger Mode Enable — This bit enables the external trigger on ATD channel 7. The external trigger
allows to synchronize sample and ATD conversions processes with external events.
0 Disable external trigger
1 Enable external trigger
Note: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode
is enabled.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
231
Rev 01.24