MC9S12C128V1 Datasheet, PDF (94/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.4.3 Port P Data Direction Register (DDRP)
Module Base + 0x001A
R
W
Reset
7
DDRP7
0
Read: Anytime.
Write: Anytime.
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 2-26. Port P Data Direction Register (DDRP)
Table 2-22. DDRP Field Descriptions
1
DDRP1
0
0
DDRP0
0
Field
Description
7–0
DDRP[7:0]
Data Direction Port P — This register configures each port P pin as either input or output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP
or PTIP registers, when changing the DDRP register.
2.3.2.4.4 Port P Reduced Drive Register (RDRP)
Module Base + 0x001B
R
W
Reset
7
RDRP7
0
6
RDRP6
5
RDRP5
4
RDRP4
3
RDRP3
2
RDRP2
0
0
0
0
0
Figure 2-27. Port P Reduced Drive Register (RDRP)
1
RDRP1
0
0
RDRP0
0
Read: Anytime.
Write: Anytime.
Table 2-23. RDRP Field Descriptions
Field
Description
7–0
RDRP[7:0]
Reduced Drive Port P — This register configures the drive strength of each port P output pin as either full or
reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
94
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24