MC9S12C128V1 Datasheet, PDF (85/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

2.3.2.2 Port S Registers
Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.2.1 Port S I/O Register (PTS)
Module Base + 0x0008
7
6
5
4
3
2
R
0
0
0
0
PTS3
PTS2
W
SCI
—
—
—
—
—
—
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-10. Port S I/O Register (PTS)
1
PTS1
TXD
0
0
PTS0
RXD
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SCI port associated with transmit pin 1 is configured as output if the transmitter is enabled and the
SCI pin associated with receive pin 0 is configured as input if the receiver is enabled. Please refer to SCI
Block User Guide for details.
2.3.2.2.2 Port S Input Register (PTIS)
Module Base + 0x0009
7
6
5
4
3
2
R
0
0
0
0
PTIS3
PTIS2
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-11. Port S Input Register (PTIS)
Read: Anytime.
Write: Never, writes to this register have no effect.
Table 2-10. PTIS Field Descriptions
1
PTIS1
0
0
PTIS0
0
Field
Description
3–0
Port S Input Register — This register always reads back the status of the associated pins. This also can be
PTIS[3:0] used to detect overload or short circuit conditions on output pins.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
85
Rev 01.24