MC9S12C128V1 Datasheet, PDF (107/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
A valid edge on input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive
samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by a single RC oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
2.4.2.6 Port J
In all modes, port J pins PJ[7:6] can be used for general purpose I/O or interrupt driven general purpose
I/O’s. During reset, port J pins are configured as inputs.
Port J offers 2 I/O ports with the same interrupt features as on port P.
2.4.3 Port A, B, E and BKGD Pin
All port and pin logic is located in the core module. Please refer to S12_mebi Block User Guide for details.
2.4.4 External Pin Descriptions
All ports start up as general purpose inputs on reset.
2.4.5 Low Power Options
2.4.5.1 Run Mode
No low power options exist for this module in run mode.
2.4.5.2 Wait Mode
No low power options exist for this module in wait mode.
2.4.5.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port P and J.
2.5 Initialization Information
The reset values of all registers are given in Section 2.3.2, “Register Descriptions”.
2.5.1 Reset Initialization
All registers including the data registers get set/reset asynchronously. Table 2-39 summarizes the port
properties after reset initialization.
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MC9S12C-Family / MC9S12GC-Family
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Rev 01.24