MC9S12C128V1 Datasheet, PDF (244/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.3.2.13.1 Left Justified Result Data
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
7
R _{BIT 9 MSB}
W ^{BIT 7 MSB}
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
3
BIT 5
BIT 3
2
BIT 4
BIT 2
1
BIT 3
BIT 1
0
BIT 2
BIT 0
10-bit data
8-bit data
Reset
0
0
0
0
0
0
0
0
Figure 8-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
R
W
Reset
7
6
5
4
3
2
1
0
BIT 1
BIT 0
0
0
0
0
0
0
10-bit data
U
U
0
0
0
0
0
0
8-bit data
0
0
0
0
0
0
0
0
Figure 8-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
8.3.2.13.2 Right Justified Result Data
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H
0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BIT 9 MSB BIT 8 10-bit data
0
0
0
0
0
0
0
0
8-bit data
0
0
0
0
0
0
0
0
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L
0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
7
R _{BIT 7}
W ^{BIT 7 MSB}
6
BIT 6
BIT 6
5
BIT 5
BIT 5
4
BIT 4
BIT 4
3
BIT 3
BIT 3
2
BIT 2
BIT 2
1
BIT 1
BIT 1
0
BIT 0
BIT 0
10-bit data
8-bit data
Reset
0
0
0
0
0
0
0
0
Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
244
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24