MC9S12C128V1 Datasheet, PDF (593/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 20 96 Kbyte Flash Module (S12FTS96KV1)
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
FABLO
W
Reset
0
0
0
0
0
0
0
0
Figure 20-16. Flash Address Low Register (FADDRLO)
In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI
and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For
mass erase, any address within the Flash array is valid to start the command.
20.3.2.10 Flash Data Register (FDATA)
FDATAHI and FDATALO are the Flash data registers.
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
FDHI
W
Reset
0
0
0
0
0
0
0
0
Figure 20-17. Flash Data High Register (FDATAHI)
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
FDLO
W
Reset
0
0
0
0
0
0
0
0
Figure 20-18. Flash Data Low Register (FDATALO)
In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all
FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash
address range.
20.3.2.11 RESERVED3
This register is reserved for factory testing and is not accessible to the user.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
593
Rev 01.24