MC9S12C128V1 Datasheet, PDF (456/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Field
1
PAOVF
0
PAIF
Table 15-22. PAFLG Field Descriptions
Description
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
Clearing this bit requires wirting a one to this bit in the PAFLG register while TEN bit of TSCR1 register is set to
one.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 register is set to
one. Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register
TSCR(0x0006) is set.
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MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24