MC9S12C128V1 Datasheet, PDF (256/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Register
Name
0x000B
ARMCOP
Bit 7
R
0
W Bit 7
6
0
Bit 6
5
0
Bit 5
4
0
Bit 4
3
0
Bit 3
2
0
Bit 2
1
0
Bit 1
Bit 0
0
Bit 0
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary (continued)
9.3.2.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f_SCM).
PLLCLK = 2xOSCCLKx₍---⁽_R--^S--_E-^Y---_F-^N--_D---^R--_V----⁺--₊--¹---₁-⁾--₎
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Module Base + 0x0000
7
R
0
W
6
5
4
3
2
0
SYN5
SYNR
SYN3
SYN2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-4. CRG Synthesizer Register (SYNR)
1
SYN1
0
Read: anytime
Write: anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
0
SYN0
0
256
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24