MC9S12C128V1 Datasheet, PDF (666/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Appendix A Electrical Characteristics
A.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
V_DDPLL
R
Cs
XFC Pin
Phase
VCO
f_osc
1
f_ref
D
KF
refdv+1
f_vco
KV
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure A-2. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K₁, f₁ and i_ch from Table A-17.
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o--}₌^-) _{–100 ⋅ e}^{(---6---–0---1-–--0---50---0---}₌⁾ _-90.48MHz/V
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
i_ch is the current in tracking mode.
= 316.7Hz/Ω
666
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24