MC9S12C128V1 Datasheet, PDF (92/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.3.6 Port M Polarity Select Register (PPSM)
Module Base + 0x0015
7
R
0
W
Reset
0
Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
PPSM5
PPSM4
PPSM3
PPSM2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-22. Port M Polarity Select Register (PPSM)
Table 2-20. PPSM Field Descriptions
1
PPSM1
0
0
PPSM0
0
Field
Description
5–0
PPSM[5:0]
Polarity Select Port M — This register selects whether a pull-down or a pull-up device is connected to the pin.
0 A pull-up device is connected to the associated port M pin, if enabled by the associated bit in register PERM
and if the port is used as input or as wired-or output.
1 A pull-down device is connected to the associated port M pin, if enabled by the associated bit in register PERM
and if the port is used as input.
2.3.2.3.7 Port M Wired-OR Mode Register (WOMM)
Module Base + 0x0016
7
R
0
W
6
5
4
3
2
1
0
0
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-23. Port M Wired-OR Mode Register (WOMM)
Read: Anytime.
Write: Anytime.
Table 2-21. WOMM Field Descriptions
Field
Description
5–0
Wired-OR Mode Port M — This register configures the output pins as wired-or. If enabled the output is driven
WOMM[5:0] active low only (open-drain). A logic level of “1” is not driven. This bit has no influence on pins used as inputs.
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
92
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24