MC9S12C128V1 Datasheet, PDF (255/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
NOTE
Register address = base address + address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
9.3.2 Register Descriptions
This section describes in address order all the CRGV4 registers and their individual bits.
Register
Name
0x0000
SYNR
0x0001
REFDV
0x0002
CTFLG
0x0003
CRGFLG
0x0004
CRGINT
0x0005
CLKSEL
0x0006
PLLCTL
0x0007
RTICTL
0x0008
COPCTL
0x0009
FORBYP
0x000A
CTCTL
Bit 7
6
5
4
3
2
1
Bit 0
R
0
W
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
R
0
0
0
0
REFDV3 REFDV2 REFDV1 REFDV0
W
R
0
0
0
0
0
0
0
0
W
R
RTIF
W
PORF
LVRF
LOCKIF
LOCK
TRACK
SCMIF
SCM
R
0
RTIE
W
0
0
LOCKIE
0
0
SCMIE
R
PLLSEL
W
PSTP SYSWAI ROAWAI PLLWAI
CWAI
RTIWAI COPWAI
R
0
CME
PLLON AUTO
ACQ
PRE
PCE
SCME
W
R
0
W
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
R
0
0
0
WCOP RSBCK
CR2
CR1
CR0
W
R
0
0
0
0
0
0
0
0
W
R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary
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MC9S12C-Family / MC9S12GC-Family
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