MC9S12C128V1 Datasheet, PDF (356/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Field
5
PCLK5
4
PCLK4
3
PCLK3
2
PCLK2
1
PCLK1
0
PCLK0
Table 12-4. PWMCLK Field Descriptions
Description
Pulse Width Channel 5 Clock Select
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
Pulse Width Channel 4 Clock Select
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Module Base + 0x0003
7
6
5
4
3
2
1
R
0
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Read: anytime
Write: anytime
NOTE
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
0
PCKA0
0
356
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24