MC9S12C128V1 Datasheet, PDF (82/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.1.2 Port T Input Register (PTIT)
Module Base + 0x0001
R
W
Reset
7
PTIT7
—
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-4. Port T Input Register (PTIT)
Read: Anytime.
Write: Never, writes to this register have no effect.
Table 2-4. PTIT Field Descriptions
1
PTIT1
—
0
PTIT0
—
Field
Description
7–0
Port T Input Register — This register always reads back the status of the associated pins. This can also be
PTIT[7:0] used to detect overload or short circuit conditions on output pins.
2.3.2.1.3 Port T Data Direction Register (DDRT)
Module Base + 0x0002
R
W
Reset
7
DDRT7
0
Read: Anytime.
Write: Anytime.
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 2-5. Port T Data Direction Register (DDRT)
Table 2-5. DDRT Field Descriptions
1
DDRT1
0
0
DDRT0
0
Field
Description
7–0
DDRT[7:0]
Data Direction Port T — This register configures each port T pin as either input or output.
The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM module port
associated with an enabled output compare. In these cases the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer input capture always monitors the state of the pin.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT
or PTIT registers, when changing the DDRT register.
82
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24