MC9S12C128V1 Datasheet, PDF (407/690 Pages) Freescale Semiconductor, Inc – MC9S12C Family MC9S12GC Family Reference Manual

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
With the misaligned character shown in Figure 13-20, the receiver counts 167 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
((167 – 160) / 167) X 100 = 4.19%
13.4.4.5.2 Fast Data Tolerance
Figure 13-21 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but is still sampled at RT8, RT9, and RT10.
STOP
IDLE OR NEXT FRAME
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 13-21. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 13-21, the receiver counts 154 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is:
((160 – 154) / 160) x 100 = 3.75%
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 13-21, the receiver counts 170 RTr cycles at the point when
the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is:
((176 – 170) / 176) x 100 = 3.40%
13.4.4.6 Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register
2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will
still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.
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